1. Field of the Invention
The present invention relates to a method of operating a semiconductor memory device, and more particularly, to a method of erasing a P-channel non-volatile memory.
2. Description of Related Art
Among various kinds of memory products, the non-volatile memory is a kind of memory characterized by the advantages for multiple data storing, reading or erasing operations. The data stored in the non-volatile memory will be retained even if the power applied to the integrated device is cut off. Hence, the non-volatile memory has become a widely adopted memory device in personal computers and electronic equipments.
In a typical non-volatile memory such as electrically erasable programmable read only memory (EEPROM), a floating gate and a control gate are formed of doped polysilicon. However, when a defect exists in a tunneling oxide layer under the doped polysilicon floating gate, current leakage will occur in the memory device and thus the reliability of the memory device is affected.
Therefore, in the recent non-volatile memory technologies, a charge-trapping layer is also used to replace a doped polysilicon floating gate. A material of the charge-trapping layer is silicon nitride, for example. The silicon nitride charge-trapping layer usually has a silicon oxide layer on its top surface and bottom surface respectively, thus forming an oxide-nitride-oxide (ONO) composite layer. The kind of device is usually called silicon/oxide/nitride/oxide/silicon (SONOS) device.
Since silicon nitride has a characteristic to trap electrons, the electrons injected into the charge-trapping layer would concentrate at a partial area of the charge-trapping layer. Hence, the sensitivity to defects in the tunneling oxide layer is lower and the phenomenon of current leakage in the device is less prone to happen.
FIG. 1 is a schematic diagram showing a method of erasing a non-volatile memory based on the prior art. In FIG. 1, the symbol “●” stands for an electron.
Referring to FIG. 1, a non-volatile P-channel memory is consisted of a substrate 100, an N-type well 102, a SONOS memory cell 104 and a select transistor 106. The SONOS memory cell 104 and the select transistor 106 are connected in series. The SONOS memory cell 104 includes a bottom oxide layer 108, a silicon nitride layer 110, a top oxide layer 112, a control gate 114, a source/drain region 116 and a source/drain region 118. The select transistor 106 includes a gate oxide layer 120, a select gate 122, a source/drain region 118 and a source/drain region 124. To perform an erasing operation, a voltage of 6 volts is applied to the source/drain region 116, N-type well region 102 and the source/drain region 124. And a voltage of 3.3 volts is applied to the select gate 122 so that a channel under the select gate 122 is turned on to equalize potentials of the source/drain regions 118 and source/drain regions 124, and a voltage of −6 volts is applied to the control gate 114 to erase the data stored in the memory cell by the Fowler-Nordheim (F-N) tunneling mechanism.
However, when using the F-N tunneling mechanism to erase data in the SONOS memory cell 104, a threshold voltage of the SONOS memory cell 104 would be decreased with erasing time. However, a voltage difference between the control gate 114 and the substrate 100 also induces electrons from the control gate 114 into the silicon nitride layer 110, resulting in gradual saturation of the threshold voltage, i.e., the so-called erasing saturation phenomenon. As a result, although the erasing time is increased, the erase performance of the device is affected.
FIG. 2 shows a relationship diagram of read current and erasing time obtained by a conventional method of erasing a SONOS memory cell. When using the F-N tunneling mechanism to erase data stored in the SONOS memory cell 104, a method of forming different voltage differences between the control gate 114 and N-type well 102 includes applying different positive voltages to the N-type well 102, the source/drain region 124 and the source/drain region 116, and applying a voltage of 3.3 volts to the select gate 122 so as to turn on a channel under the select gate 122 and to equalize potentials of the source/drain region 118 and the source/drain region 124. A symbol “●” represents applying a voltage of −5.5 volts to the control gate 114, a symbol “▴” represents applying a voltage of −6 volts to the control gate 114, and a symbol “∇” represents applying a voltage of −6.5 volts to the control gate 114. As shown in FIG. 2, when the voltages applied to the control gate 114 are −5.5 volts, −6 volt and −6.5 volts, due to electrons from the control gate injecting into the charge-trapping layer, even if the time of erasing operation is prolonged, read currents still cannot be rapidly reduced. The erase performance is degraded after certain erase time.
Also, as integrity of the device increases, in order to enhance a tunneling efficiency of electrons, a bottom oxide layer of a memory would need to be thinner. Poor charge retention performance becomes a concern when compared to thicker bottom oxide. Hence, it may need longer development time for trade-off between the erase performance and reliability concerns such as charge retention.